I think Craig has just very neatly summarised the age-old RISC vs CISC debate:
A RISC has fewer, simpler instructions, so each instruction does less and executes quicker - but you need more of 'em to accomplish the task!

Raw MIPS figures have never been a very good indicator of relative processor performance, but comparisons of RISC MIPS against CISC MIPS are totally worthless - apples and oranges!