When using SRAM chips it is best that you arrange your interface to completely terminate one cycle before you start another. However <big><big>IF</big></big> you are sure the R/W line to the SRAM stays high in the READ state then it is OK to change address to go to another read location while CS (chip select) stays low, Although I would not do it. During writing cycles it is quite another thing however. If you change address while R/W is in WRITE state and CS is still low you will cause many problems of partially writing many locations in the SRAM.

If your issue is one of speed with your 8051 and you are concerned with the amount of time it takes to transfer a whole block of data out of the SRAM into 8052 then consider this option. Do not supply the address to the SRAM directly from the 8051. Instead put a counter in the CPLD to provide the address and let the 8051 simple cycle CS cycle by cycle. Use the end of the CS signal (when it goes high to cause the counter to increment). Of course you need a way also for the 8052 to initialize the address, either with a clear to the counter so 8051 always starts blobk with address 0000H or some way to load address counter. The byte wide inteface to the SRAM implies that you have these lines available to the 8051 so a simple upper address decoder in the CPLD can provide a couple of ports as registers in the CPLD to load the address counter to a specified start location.

In the above I have presumed you connected the SRAM to the port pins and have the uP software accessing the RAM via the ports. You could also consider using the external BUS mode of the 8051 to access the SRAM. This would be quite a bit faster and then address and data can be quickly updated in one cycle.

Mike Karas