jay jay:
In terms of the SRAM reading in your CPLD. I would simplify your design by having 2 chips side by side. Have CPLD read out 16 bits from 2 chips at once. In this way you only need to make 1 read cycle intstead of 2. Make the 8051 part where the RAM is written be the more complicated part becasue it is easier to split the data in software than to try to join it in hardware.

I also think that you have lots of time. You mentioned you have 100 nSec SRAM. But you have cycle time of 2 uSec (== 2000 nSec). It should be VERY VERY easy to make CPLD have a state machine to read a memory word 16-bits within this time and still support having CS go on and off for each cycle. You just need to use a little faster clock to the CPLD is all so that the state machines in the CPLD came do things quickly. Most of the smaller CPLDs that I have worked with will work well with 20 MHz clock. With this speed you can have state changes every 50 nSec. And you can make up to 40 state machine clocks within one of your 2 uSec cycle times. I cannot imagine why you have a time performance problem!! In fact @100 nSec RAM access time yo8 have plenty of time to read two samples from 8 bit wide RAM and combine them into your 12-16 bits and have time left over before next cycle starts. Now if you were clocking your CPLD @ 1 MHz you would have a problem. By the way I think for your application that even 5 MHz to the CPLD would be too slow....Look at 20 MHz..you will zip along.

Mike Karas