Good idea if the cost factor for a dual ported SRAM is not a problem. Could even save on cost if the cost of CPLD is considered because dual port RAM would make the amount of CPLD logic come down. The dual ported SRAMs are definately a clean way to eliminate most problems.

Jay Jay, Even if you go this route you will have to consider the issue of having the read out circuit know when the 8052 has completed the writing of the data. This can be handled with a dual port RAM via the "flags" register these chips have. Some chips even have a convenient interrupt signalling pin from one side to the other (which does not need to be used as a processor interrupt in the classic sense). With such an interrupt output the 8052 on the writing side could set its flag and assert the interrupt to your readout circuit to trigger it to go.
Mike