Hi Jay Jay,
I've recently done something similar to what you are attempting. I used a Lattice CPLD and a Cygnal C8052F226 and two 8bit wide 32kbyte memory chips for an A/D system. Since my A/D is 100kS/s maximum, I set up a dedicated write-window every 10nS. Since I don't need truly random access to the SRAM, I used two 16bit counters in the CPLD as address controllers, and muxed their outputs to the memory address output lines. When not writing, the CPLD reads in 16bits and signals the 8051 that it has data available. Once the 8051 reads the data out, it signals the CPLD which causes a read address increment, a new read, and then a data read signal. With the reading of memory, I also set up dedicated read-windows within the non-write time. This is done with everything run on a 24MHz clock. Memory CS is always selected, and it works nicely. One thing I would note about this is that I ran seperate I/O lines between the CPLD and the memory chips, so it's a 16bit write, but an 8 bit read because I'm ultimately going to an 8bit USB tranceiver. It was easier to use the LSB of the read-address counter to control the output mux. Hope this helps.
-Josh