Hi
Michale thanks for your reply.

i will give some details about design .

89c52 will only write data into memory and will not read so interfacing is normal with
rd/,wr/ signal.

but the same location will be read by cpld and all control signals & address to ram will
generated by cpld itself, as I have to read 12 to 16 bytes with in 2us. time is important factor. if i don’t toggle the ce,oewhile reading (cpld will only read) my 2time period in every read cycle will be saved. this all i need to design cpld.

your suggestions are welcome