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???
04/28/03 15:47
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#44431 - Nitpicking schematics
Responding to: ???'s previous message
Guys, this is crazy. Firstly, the schematic was shown as an example. Is it necessary to analyze an academic example so closely? What kind of ground potential problems will there be - isn't that heavily dependent on current and resistance in the ground network?

Secondly, the schematic provides a netlist, not component placement and routing. I pitty the engineer that places all his bypass caps next to the regulator because thats how the schematic shows it.

- Lee

List of 30 messages in thread
TopicAuthorDate
Dinamic time delay            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
      RE: Dinamic time delay            01/01/70 00:00      
         RE: Dinamic time delay            01/01/70 00:00      
            RE: Dinamic time delay            01/01/70 00:00      
               RE: Dinamic time delay, Michael            01/01/70 00:00      
               RE: Dinamic time delay            01/01/70 00:00      
                  RE: Dinamic time delay            01/01/70 00:00      
               Nitpicking schematics            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
      RE: Dinamic time delay            01/01/70 00:00      
         RE: Dinamic time delay            01/01/70 00:00      
         RE: Dinamic time delay            01/01/70 00:00      
            RE: Dinamic time delay            01/01/70 00:00      
               RE: Dinamic time delay            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
      RE: Dinamic time delay. Rob            01/01/70 00:00      
         RE: Dinamic time delay. Rob            01/01/70 00:00      
            RE: Dinamic time delay. Rob            01/01/70 00:00      
               RE: And Kai...............            01/01/70 00:00      
               RE: Dinamic time delay. Rob            01/01/70 00:00      
               RE: Dinamic time delay. Rob            01/01/70 00:00      
                  RE: Dinamic time delay. Rob            01/01/70 00:00      
                     RE: Dinamic time delay. Rob            01/01/70 00:00      
                        RE: Dinamic time delay. Rob            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
      FPGA            01/01/70 00:00      

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