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???
05/01/03 18:50
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#44644 - RE: Dinamic time delay
Responding to: ???'s previous message
Back to main subject guys. To Jose Orlando, you can measure a clock period easy in FPGA, if you familiar with those. Basic, you need a fast reference clock, build a counter to count from
edge to edge of the input clock, knowing your
reference period and the counted value you can figure out input clock period.



List of 30 messages in thread
TopicAuthorDate
Dinamic time delay            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
      RE: Dinamic time delay            01/01/70 00:00      
         RE: Dinamic time delay            01/01/70 00:00      
            RE: Dinamic time delay            01/01/70 00:00      
               RE: Dinamic time delay, Michael            01/01/70 00:00      
               RE: Dinamic time delay            01/01/70 00:00      
                  RE: Dinamic time delay            01/01/70 00:00      
               Nitpicking schematics            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
      RE: Dinamic time delay            01/01/70 00:00      
         RE: Dinamic time delay            01/01/70 00:00      
         RE: Dinamic time delay            01/01/70 00:00      
            RE: Dinamic time delay            01/01/70 00:00      
               RE: Dinamic time delay            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
      RE: Dinamic time delay. Rob            01/01/70 00:00      
         RE: Dinamic time delay. Rob            01/01/70 00:00      
            RE: Dinamic time delay. Rob            01/01/70 00:00      
               RE: And Kai...............            01/01/70 00:00      
               RE: Dinamic time delay. Rob            01/01/70 00:00      
               RE: Dinamic time delay. Rob            01/01/70 00:00      
                  RE: Dinamic time delay. Rob            01/01/70 00:00      
                     RE: Dinamic time delay. Rob            01/01/70 00:00      
                        RE: Dinamic time delay. Rob            01/01/70 00:00      
   RE: Dinamic time delay            01/01/70 00:00      
      FPGA            01/01/70 00:00      

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