| ??? 05/01/03 18:50 Read: times |
#44644 - RE: Dinamic time delay Responding to: ???'s previous message |
Back to main subject guys. To Jose Orlando, you can measure a clock period easy in FPGA, if you familiar with those. Basic, you need a fast reference clock, build a counter to count from
edge to edge of the input clock, knowing your reference period and the counted value you can figure out input clock period. |



