| ??? 06/19/03 21:17 Read: times |
#48859 - RE: Multiplex P0 for I/O and XRAM access Responding to: ???'s previous message |
Thanks guys!
Using a PLD to do memory mapped I/O or a uC with more I/Os available is certainly an engineering solution, but I am afraid that I may not have the luxury in terms of the product cost. As to what Joe said, in my first failed attempt, I remember that I tried writing 0x00 or 0xFF to P0 after reading from the tri-stated buffer (74HC244) or writing to the latch (74HC573) to free up the internal bus and it still didn't work. |
| Topic | Author | Date |
| Multiplex P0 for I/O and XRAM access | 01/01/70 00:00 | |
| RE: Multiplex P0 for I/O and XRAM access | 01/01/70 00:00 | |
| RE: Multiplex P0 for I/O and XRAM access | 01/01/70 00:00 | |
| RE: Multiplex P0 for I/O and XRAM access | 01/01/70 00:00 | |
| RE: Multiplex P0 for I/O and XRAM access | 01/01/70 00:00 | |
| RE: Multiplex P0 for I/O and XRAM access | 01/01/70 00:00 | |
| RE: Multiplex P0 for I/O and XRAM access | 01/01/70 00:00 | |
| RE: Multiplex P0 for I/O and XRAM access | 01/01/70 00:00 | |
| Correction | 01/01/70 00:00 | |
| RE: Correction/K. Klaas | 01/01/70 00:00 | |
RE: Correction/K. Klaas | 01/01/70 00:00 | |
| RE: Multiplex P0 for I/O and XRAM access | 01/01/70 00:00 | |
| RE: Multiplex P0 for I/O and XRAM access | 01/01/70 00:00 |



