After re-reading my last post, I realized, that some misinterpretatian can result. I do not want to recommend the circuit consisting of only two OR gates, but only show how decoding 'can' be done and 'is' done sometimes. But I would only use foolproof decoding, where address lines can show any data without resulting in bus contention. I apologize for being not clear enough in this point!

As I stated in my last post, 74HC138 can help in preventing bus contention. Connect three inputs A,B and C of 74HC138 to address lines A13, A14 and A15. Now, connect one of the 8 outputs of 74HC138 to CE# input of 8kByte Data Ram. Connect one OTHER output of 74HC138 to input of OR gate (strobing 74HC574), which was connected to A15. Finally, connect one THIRD output of 74HC138 to input of OR gate (strobing 74HC541), which was connected to A15. So, three different outputs of 74HC138 go to RAM and to the two OR gates. WR# and RD# lines remain unchanged.

OR gate used for strobing 74HC541 is not really necessary, because G1# and G2# inputs do the same. But if instead of 74HC541 a 74HC240 is used, OR gate is necessary. If 74HC541 is definitely used, connect output of 74HC138 directly to G1# input of 74HC541 and connect RD# line directly to G2# input of 74HC541.

OR gates can totally be omitted, when 74HC377 is used instead of 74HC574. Then, connect output of 74HC138 to G# input of 74HC377 and WR# line directly to CLK input of 74HC377.
So, when using 74HC541 and 74HC377, only one 74HC138 is needed for accessing RAM and additional input and output ports, and bus contention is securely prevented.

Bye,
Kai