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???
06/20/03 03:12
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#48862 - RE: Multiplex P0 for I/O and XRAM access
Responding to: ???'s previous message
Hallo Alan,

from a theoretical point of view it's possible to do this. But it makes no sense! The big advantage of a mcu having many ports is, that you need not to have them interfaced by memory mapping. But if you already do memory mapping, because you must do it for accessing some external
memory, why not interfacing of any other inputs or outputs by also doing memory mapping?
Assume that you have a 8kByte RAM interfaced by memory mapping and still want to have an input port and output port, then you could use the following scheme for accessing them via memory mapping. The only thing you need is two OR gates of 74HC32:



As you still have two OR gates of 74HC32 you can implement an additional input port and output port. Then, take A14 for gating. Take care, that A13, A14 or A15 do never have low level together, at the same time. So, only the following addresses are allowed: 011X,XXXX,XXXX,XXXX, 101X,XXXX,XXXX,XXXX and 110X,XXXX,XXXX,XXXX.
Of course, you can also use 74HC138, then even more input ports and output ports can be accessed and bus contention is securely prevented.

Bye,
Kai

List of 13 messages in thread
TopicAuthorDate
Multiplex P0 for I/O and XRAM access            01/01/70 00:00      
   RE: Multiplex P0 for I/O and XRAM access            01/01/70 00:00      
   RE: Multiplex P0 for I/O and XRAM access            01/01/70 00:00      
      RE: Multiplex P0 for I/O and XRAM access            01/01/70 00:00      
         RE: Multiplex P0 for I/O and XRAM access            01/01/70 00:00      
   RE: Multiplex P0 for I/O and XRAM access            01/01/70 00:00      
      RE: Multiplex P0 for I/O and XRAM access            01/01/70 00:00      
         RE: Multiplex P0 for I/O and XRAM access            01/01/70 00:00      
      Correction            01/01/70 00:00      
         RE: Correction/K. Klaas            01/01/70 00:00      
            RE: Correction/K. Klaas            01/01/70 00:00      
      RE: Multiplex P0 for I/O and XRAM access            01/01/70 00:00      
         RE: Multiplex P0 for I/O and XRAM access            01/01/70 00:00      

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