The IDT7130 also has a very handy interrupt signaling functionality built right in. Using this facility the right side can write to location 0x3FE and assert the interrupt handshake to the left side. This handshake can be connected to one of the external interrupt pins of the left side 8051. The left side 8051 can terminate the interrupt stimulus by reading from its 0x3FE address.

In a similar manner the left side can send an interrupt handshake to the right side. The left side writes to location 0x3FF which caused the right side interrupt signal to be asserted. The right side 8051 would have this connected to one of its external interrupt pins. The right side 8051 removes the interrupt stimulus by reading from its 0x3FF address.

The SRAM bytes used with this system can be used as a mailbox to send user defined data bytes across to the other processor. Using this scheme the initiating side writes to cause the mailbox to be loaded and an opposite side interrupt to occur. The target side then reads the mail box (whilst also clearing the stimulus as described above) and uses the mailbox info as defined by the programmer.

I have used this scheme several times to hand buffer status in the rest of the DUAL PORT RAM back and forth between the processors. In those applications the rest of the SRAM was divided into pairs of buffers (for example 2 buffers or 4 buffers). One buffer in each pair is used to transfer data from left to right and the other one used to pass data right to left. A buffer is always completely written by one side before the other side is permitted to start reading it.

It works nice to let a bit in the mail box interrupt bytes be a signal that a buffer is ready. The reason this works so well is that the target processor can be interrupted as to when the data is ready instead of the target 8051 having to poll some status byte.

Michael Karas