| ??? 11/20/03 08:38 Read: times |
#59084 - RE: Dual Port Ram memory problems Responding to: ???'s previous message |
No polling or time delay waiting is necessary....... Sending processor generated the mailbox interrupt AFTER the data data is ready. The receive end will see the buffer ready via the interrupt and the buffer bit being set int he mailbox byte. The receiver of the interrupt will manage the transfer of data out of the buffer and then clear the mail box bit and then send an interrupt back to the originating processor. The first one sees the buffer bit now cleared in the mailbox location it will now know that the buffer is once again free to be filled again.
Michael Karas |
| Topic | Author | Date |
| Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
| RE: Dual Port Ram memory problems | 01/01/70 00:00 | |
RE: Dual Port Ram memory problems | 01/01/70 00:00 |



