"The reason this works so well is that the target processor can be interrupted as to when the data is ready instead of the target 8051 having to poll some status byte. "

Micheal how will the target processor or reading 8051 in my case come to know that the data is written completely.

The reading 8051(left side) will clear the interrupt by reading location 03FEh and start reading. So does it mean that ,if the left side 8051 gets interrupt by the writing 8051 on right side ,it will have to wait for a specified time and then clear the interrupt and read it.

Thanks,
Pravin