I've encountered a bit of a corner case in the 8051 architecture, and want to make sure that I've got the right take on things; input from anyone who's been there would be appreciated.

I'm working on an application whose power constraints are such that I want to put the processor (a Cygnal 'F12x) into Idle mode whenever possible. So, I'm wanting to go with an event driven software architecture, where some interrupts herald the arrival of an event and thus require the execution of some base level (non-interrupt service routine) code following the completion of the ISR, and other interrupts don't and thus the processor should just go back to sleep at ISR completion. E.g., the SPI byte completion interrupt is 'eventful' only if the given byte is the final byte of a multibyte transaction.

So, to implement this, I'll have some manner of data structure shared between the ISR level and the base level that serve to convey the 'eventfulness' semantic from the ISR to the 'wakeup' code, which, upon examination of said structure, decides to either a) go back to sleep or b) go execute the event handler. In the latter case, other eventful interrupts may occur during the event handler, and so upon returning from it the 'wakeup' code again consults the data structure and maybe repeats the process.

Eventually, though, it runs out of work (or never had any in the first place), and wants to go to sleep. since I don't want this code to miss any eventful interrupts in between deciding to go to sleep and actually doing so, it needs to disable interrupts when consulting the data structure, and thus will need to traverse from the {interrupt disabled, full power} state to the {interrupt enabled, idle} state in a fashion that is atomic with respect to interrupts.

And so, the question: how to do this? From reading The Ancient Text, I note that, once an interrupt is captured by the hardware, the actual vectoring to an ISR is deferred for as long as the next instruction in the current execution stream consists of RETIs or writes to IE or IP, and additionally for one more instruction. My understanding from the above is that one could just set the EA bit to reenable interrupts and then write to PCON to induce Idle mode, and thus the first interrupt opportunity would be immediately after the PCON write and consequential entry to Idle mode, such that Idle mode is in effect only for the instant in between the PCON write and the jump to the vector table.

So, did I interpret the runes correctly and it is thus this simple (particularly for the given platform), or do I need to get more creative? And if so, then again: how?

Thanks in advance,
David