Michael, thanks for responding. While one could easily test some aspects of this problem, e.g. that the part did reach the {interrupt enabled, idle} state, I don't see, via testing, trying to absolutely confirm that interrupts are never taken during the interval as feasable, due to the asynchronous relationship of potential interrupt assertion and the system clock; the set of test vectors is infinite.

Though I thought it useful to start here, I may well have to go to Cygnal with this question, as the 'F12x datasheet, though in section 12.0 claiming the part to be "fully compatible with the MCS-51 instruction set", whatever that means, does not explicitly confirm, in 12.7, identical behavior in this area; indeed, 12.7.4 does not at all mention writes to IE and IP as delaying interrupt vectoring (rather, it only mentions that execution of a RETI guarantees execution of the next instruction).

David