| ??? 02/10/04 00:10 Read: times |
#64360 - RE: ashish pradhan Responding to: ???'s previous message |
http://www.analog.com/UploadedF...7866_a.pdf
the part is the ad7866 a dual 12 bit sar adc.again i am providing the serial clock via the 8051 by setting and clearing a port pin p3.2 repeditively 32 times.this is the only way of controlling the part as the data sheet requires that the sclk go low a specified time after the cs (start conversion which causes the front end sample and hold amplifier to sample the signal.(this means i must use a burst clock).i cannot think of any other way of generating the clock by software! |
| Topic | Author | Date |
| adc interfacing. | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 | |
| UART Shift Register mode | 01/01/70 00:00 | |
| Read each bit in turn | 01/01/70 00:00 | |
| RE: andy neil | 01/01/70 00:00 | |
| RE: andy neil | 01/01/70 00:00 | |
| RE: andy neil | 01/01/70 00:00 | |
| RE: Read each bit in turn | 01/01/70 00:00 | |
| RE: michael neary | 01/01/70 00:00 | |
| RE: Read each bit in turn | 01/01/70 00:00 | |
| RE: Read each bit in turn | 01/01/70 00:00 | |
| RE: Read each bit in turn | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 | |
| Correction: | 01/01/70 00:00 | |
| RE: ashish pradhan | 01/01/70 00:00 | |
| RE: ashish pradhan | 01/01/70 00:00 | |
| RE: ashish pradhan | 01/01/70 00:00 | |
| RE: ashish pradhan | 01/01/70 00:00 | |
| RE: ashish pradhan | 01/01/70 00:00 | |
RE: ashish pradhan | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 |



