| ??? 02/10/04 00:50 Read: times |
#64362 - RE: Read each bit in turn Responding to: ???'s previous message |
each output bit of the adc is only present on the falling edge of the sclk provided to the adc by the microcontroller Strictly speaking, not true; and that is where your confusion is. Each output bit is present from (very) shortly after the rising edge of the clock until (very) shortly after the next rising edge. When sclk is at maximum speed, this is similar in meaning to "present only on the falling edge". At lower speeds, the above description is correct. |
| Topic | Author | Date |
| adc interfacing. | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 | |
| UART Shift Register mode | 01/01/70 00:00 | |
| Read each bit in turn | 01/01/70 00:00 | |
| RE: andy neil | 01/01/70 00:00 | |
| RE: andy neil | 01/01/70 00:00 | |
| RE: andy neil | 01/01/70 00:00 | |
| RE: Read each bit in turn | 01/01/70 00:00 | |
| RE: michael neary | 01/01/70 00:00 | |
| RE: Read each bit in turn | 01/01/70 00:00 | |
| RE: Read each bit in turn | 01/01/70 00:00 | |
| RE: Read each bit in turn | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 | |
| Correction: | 01/01/70 00:00 | |
| RE: ashish pradhan | 01/01/70 00:00 | |
| RE: ashish pradhan | 01/01/70 00:00 | |
| RE: ashish pradhan | 01/01/70 00:00 | |
| RE: ashish pradhan | 01/01/70 00:00 | |
| RE: ashish pradhan | 01/01/70 00:00 | |
RE: ashish pradhan | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 | |
| RE: adc interfacing. | 01/01/70 00:00 |