at the moment i am currently in the process of trying to use the same clock as, supplied to the adc (inverted) -for use with a positive edge 8 bit serial to parallel shift reg connected to the output of the adc and read a whole port every eight clock pulses.this will require four reads for each conversion- 32 clk pulses bit stream ->16 clk pulses for each adc with the two adc results on the same output pin giving 32 clk pulses . i will the have eight clock pulses inbetween reads in which i must store the data in memory.this is just an idea i will get back tomorrow evenging or so with the result.im trying anything at this stage.with this method the clock for the adc and the shift reg will be synchronous! dose anyone see any problems with this, method????