Apart from the trigger and the sampling rate,having the sram and r#the cpld seperate doesnt make a lot of sense,it would be better to use a fpga with lots of embedded sram such as the xilinx virtexII to implement the fifo.

Thanks for your reply.


You are right Jez. FPGA can be used here and there are several projects on net using FPGA for scope. But these FPGA's are not easily available in Mumbai whereas a CPLD is available easily and fairly cheap. Even RS India doesn't have Virtex II or Spartan II / III listed on their site. They have XC3xxx, XC4xxxx, XCS5/5XL and XCS10XL not sure if the 5000 gates that I get in XCS5XL will be enough for my application I need to store 256 samples each 8 bits and the logic for trigeering and ADC reading too has to be incorporated in FPGA.

Regards,
Prahlad Purohit