Hallo Prahlad,

sounds interesting! But keep in mind, that special knowledge in designing HF analog circuits is needed!

At input you need a very carefully dimensioned voltage divider providing frequency compensation of stray inductance and stray capacitance of involved divider parts. Another problem is the section where you switch inside this divider to provide selection of wanted input voltage sensitivity. This switching arrangement must also be included in your frequency compensation!
Another problem is, that you need a buffer with stable gain at input. A buffer which must show stable and reliable performance well above your wished sampling rate of 100MHz, free of any ringing!!! Only a handful of chips are suited at this point!

Another point is the 'trigger'. 'Triggering' means, that all plot snippets of a periodical curve do exactly overlap! When sampling with 100MHz, then no trigger jitter of more than a few nanoseconds is allowed!! This means that you need a precision comparator where all the propagation delay uncertainties resulting in jitter must not be above 3-4nsec. And it means, that comparator must show a repeatability of about 1-2nsec, assuming, that comparator is not the only part making the trigger section.
The problem with the comparator is, that there must not even exist the least amount of noise on ground and Vcc at comparator, because this noise would immediately be transformed into trigger jitter! But how to accomplish this, remember the comparator IS digital at its output and you HAVE to deal with digital noise on ground!! Here, you reach the limits of physics...

To design proper input and trigger stages counts to the most difficult and sophisticated challenges you can imagine!!
And by all these difficulties you probably will not have any reference scope to test what you design, am I write? This is like doing a heart operation with closed eyes...

But nevertheless, sounds exciting!!

Good luck,
Kai