Hello,

This is an asci art of the situation:

parallel bus
master <------------------------------------------------>
| | |
S S S
l l l
a a a
v v v
e e e



1.The master will be ARC 8-bit processor.(need more arithmetic power here)
2.The slave will be 8051 like processors from Atmel and decoder for the address.
3.The bus is 8bit data/address + 7 handshake and control signals. (bus lires are shorter then 50sm. And frequency is < 1Mhz)

The problem is that the slaves will be 10 or more(32 is acceptable maximum). This mean about 2 loads on each slave(processor and decoder).

In the hardware manual of at89c4051 & 80s52, all I see is the maximum drive power (4 tsttl loads), byt lat is the consumation. Are atmel 8051 ports are CMOS stile or TTL, and lat is the maximum number that i can conekt on one lire.


Is it a good idea, all slaves to be separated from the bus with 3-state bus transciever like 74hct245 to protect the bys from overload.(adding some latency)


This is my first big project (with a lot of cpu-s and other stuff), so accept my apologize if my questions sound stupid or trivial.

Any suggestions are welcome.