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???
12/07/04 18:07
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#82710 - suggestion
Responding to: ???'s previous message
bus lires are shorter then 50sm. And frequency is < 1Mhz) .... slaves will be 10 or more(32 is acceptable maximum). This mean about 2 loads on each slave(processor and decoder).

In the hardware manual of at89c4051 & 80s52, all I see is the maximum drive power (4 tsttl loads), byt lat is the consumation. Are atmel 8051 ports are CMOS stile or TTL, and lat is the maximum number that i can conekt on one lire.


The first question is "how are you going to connect 32 (33) processors with lines "shorter then 50sm" (I assume "sm" is "cm")

If you are going to connect that many processors, I suggest you leave the derivatives you mention and choose some that can have the ports configured. If you configure all as open collector, the only limit in bus load will be capacitive. Even better, if you configure all as default OC and reconfigure the transmitting processor to push-pull for the time of transmit, I think you can make this work with a very acceptable throughput.

Examples of configurable port processors: all or most SILabs derivatives and the Philips LPC series.

Just out of curiousity hwat is your "first big project" supposed to do?

Erik




List of 22 messages in thread
TopicAuthorDate
Master / slave parallel bus            01/01/70 00:00      
   suggestion            01/01/70 00:00      
      info            01/01/70 00:00      
         config ports            01/01/70 00:00      
            serial parallel ?            01/01/70 00:00      
               various            01/01/70 00:00      
                  atmel port 0            01/01/70 00:00      
                     Port 0 as communicator            01/01/70 00:00      
                        Sorry, did not look            01/01/70 00:00      
                           reply            01/01/70 00:00      
                           supplier..            01/01/70 00:00      
                              speed            01/01/70 00:00      
                                 go on            01/01/70 00:00      
                                    to the above            01/01/70 00:00      
                                       Re: to the above            01/01/70 00:00      
                                          open collector push-pull no way            01/01/70 00:00      
                                             open collector and upsh-pull            01/01/70 00:00      
                                                push pull drive, OC receive            01/01/70 00:00      
   How to post ASCII Art            01/01/70 00:00      
   All in one chip!            01/01/70 00:00      
   Why parallel ?            01/01/70 00:00      
   CAN or cannot            01/01/70 00:00      

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