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???
12/14/04 23:16
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#83108 - go on
Responding to: ???'s previous message

Then go parallel. Have a lot of fun getting the '245s synchronized, remember that you can NEVER have 2 that simultaneously output to the bus, not even for a nanosecond. In this respect, do not forget that port pins are high during reset, you may need inverters on the pin that drives the direction.


Yes your right ... i just think what did i fogret ...If i don't want to blow out everything i will need inverters ...


To obtain 400kbyte, you also need better than 'plain vanilla' '51s since a 12 clocker running 12 MHz can never communicate at 400 kByte.

just see (even assuming the recepient respond immediately, which you can NOT assume)
fetch data 2
inc ptr 2
data on bus 1
set clock 1
test accept 2
clr clock 1
loop 2


A total if 11 clock cycles. So for a 12 clocker you will need 12 * 400k *11 = 52.8 MHZ min clock and the at89c4051 & 80s52 you mention can not run that fast.

Do not forget calculations as above before you put hardware together.


I say 400kbyte as max.(USB gave me 3mbit and this is my external bys speed). I don't need that fast device now, byt the main goal in this project is to end with one very open platform for developing extending end experimenting. The master microcontroller definitely will be (~1 op. per clock). And in some distant time there can be some faster slaves (byt for now i dont need to go so faster than 1/2Mops(per slave) for controlling the mottors and reading some sensors).

I spend almost 3 weeks in calculations. And i think that it is time to trow all the papers and start from the beginning.


What if i trow out the idea for single internal bus. I can use SPI for the slower devices. And to prepare a fast parallel bus (open collector with push-pull transmitter) for the faster devices. Ore something like that.

I am widely open for new ideas. I think that in my previous posting i post some info about the project, so please don't hesitate to offer me your proposals and ideas.


List of 22 messages in thread
TopicAuthorDate
Master / slave parallel bus            01/01/70 00:00      
   suggestion            01/01/70 00:00      
      info            01/01/70 00:00      
         config ports            01/01/70 00:00      
            serial parallel ?            01/01/70 00:00      
               various            01/01/70 00:00      
                  atmel port 0            01/01/70 00:00      
                     Port 0 as communicator            01/01/70 00:00      
                        Sorry, did not look            01/01/70 00:00      
                           reply            01/01/70 00:00      
                           supplier..            01/01/70 00:00      
                              speed            01/01/70 00:00      
                                 go on            01/01/70 00:00      
                                    to the above            01/01/70 00:00      
                                       Re: to the above            01/01/70 00:00      
                                          open collector push-pull no way            01/01/70 00:00      
                                             open collector and upsh-pull            01/01/70 00:00      
                                                push pull drive, OC receive            01/01/70 00:00      
   How to post ASCII Art            01/01/70 00:00      
   All in one chip!            01/01/70 00:00      
   Why parallel ?            01/01/70 00:00      
   CAN or cannot            01/01/70 00:00      

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