I doubt the wide data bus of SIMM/DIMM can be used easily with a '51; it also means the FPGA needs to have more pins. What I think Jez meant was to use a single SDRAM chip, which IS commercially available (or you can desolder it from a SIMM/DIMM if you want) and comes (besides other) in a 8bit wide form. It is as small as a SRAM, but the FPGA will not be too small nor cheap (and you need to feed it with a bitstream, so you might need a configuration memory, too).
You also mentioned code execution from the big RAM; this is slightly different than MOVX (tighter timing requirement - although this should pose no problem with a 100MHz rated SDRAM...). This makes also the superfast SiLabs '51 clones (and also a couple of other) unusable, as they have no support for external code memory.
On the other hand, all you might need to drive the 4 SRAMs is 1 (one) 74xx573 latch (plus the standard address latch) and a spare pin on the '51 to latch the latch :-) You would connect the D lines of latch to P2, Q0..Q3 to A15..A18 of the memories and Q4..Q7 to CS's of the 4 SRAMS (replacing the address decoder); then you will switch the (32k) banks in the "core" code memory of the controller by writing the proper page address (with only one 0 in the upper part of it) and toggling a pin.

Jan Waclawek