| ??? 03/16/05 19:55 Read: times |
#89800 - ACKs Responding to: ???'s previous message |
Oh, yeah, you might want to implement a data-acknowledge scheme using an output port on each micro. After a micro is interrupted, the ISR would obviously read the incoming mailbox and then assert its ACK output. That could drive the other micro's other external interrupt pin, or it could be polled. Once the sending micro gets the ACK, it knows that it can write new data to the mailbox.
-a |
| Topic | Author | Date |
| Contemplating multiprocessor | 01/01/70 00:00 | |
| fifo | 01/01/70 00:00 | |
| and also | 01/01/70 00:00 | |
| multiprocessor communication | 01/01/70 00:00 | |
| ACKs | 01/01/70 00:00 | |
| You want it all and you want it for free | 01/01/70 00:00 | |
| Why not HW I2C or SPI | 01/01/70 00:00 | |
| Why not HW I2C or SPI | 01/01/70 00:00 | |
| USB ??? | 01/01/70 00:00 | |
| USB !!! | 01/01/70 00:00 | |
| USB | 01/01/70 00:00 | |
| You Correct Sir | 01/01/70 00:00 | |
| USB != I2C | 01/01/70 00:00 | |
USB > I2C | 01/01/70 00:00 | |
| do not multimaster | 01/01/70 00:00 | |
| hmm | 01/01/70 00:00 | |
| concurrence | 01/01/70 00:00 | |
| This is why | 01/01/70 00:00 | |
| depends on data rate | 01/01/70 00:00 | |
| Normally | 01/01/70 00:00 | |
| Are You Sure | 01/01/70 00:00 | |
| I would be | 01/01/70 00:00 | |
| I would be | 01/01/70 00:00 | |
| it works for me | 01/01/70 00:00 | |
| Are You Sure | 01/01/70 00:00 | |
| IIC speed - no limit | 01/01/70 00:00 | |
| nixed by other team members | 01/01/70 00:00 | |
| Multi-Proc Xface | 01/01/70 00:00 | |
| exactly | 01/01/70 00:00 | |
| Shift register (Mode 0)? | 01/01/70 00:00 | |
| Time savers | 01/01/70 00:00 |