| ??? 03/16/05 20:51 Modified: 03/16/05 20:53 Read: times |
#89805 - concurrence Responding to: ???'s previous message |
This uses a lot of pins and then there is the issue of simultaneous bus requests.
The problem you are going to run into is concurrence. I have seen several schemes fail when both wanted access in the same nanosecond. One scheme I have seen work is a shared RAM and signalling as follows: uCa out to uCb edge triggered int is signal AACT uCb out to uCa edge triggered int is signal BACT At power up (common reset required) pull AACT and BACT low, do the rest of the stuff, then ints are set to edge, cleared and enabled When A want to send data to b it test BACT for low, raise AACT and write the message to RAM, lowering AACT will tell b (interrupt) that a message is present. The opposite can be figured out for B to A. concurrence is resolved by B, after testing AACT low wait some cycles (derivative dependent), and if AACT now high b will wait for the interrupt before writing the message and lowering BACT. The interrupts must be the ONLY high priority ints. Erik If you need "independent" RAM, use a chip like the 668, the internal 8k RAM will not affect the other uC. |
| Topic | Author | Date |
| Contemplating multiprocessor | 01/01/70 00:00 | |
| fifo | 01/01/70 00:00 | |
| and also | 01/01/70 00:00 | |
| multiprocessor communication | 01/01/70 00:00 | |
| ACKs | 01/01/70 00:00 | |
| You want it all and you want it for free | 01/01/70 00:00 | |
| Why not HW I2C or SPI | 01/01/70 00:00 | |
| Why not HW I2C or SPI | 01/01/70 00:00 | |
| USB ??? | 01/01/70 00:00 | |
| USB !!! | 01/01/70 00:00 | |
| USB | 01/01/70 00:00 | |
| You Correct Sir | 01/01/70 00:00 | |
| USB != I2C | 01/01/70 00:00 | |
USB > I2C | 01/01/70 00:00 | |
| do not multimaster | 01/01/70 00:00 | |
| hmm | 01/01/70 00:00 | |
| concurrence | 01/01/70 00:00 | |
| This is why | 01/01/70 00:00 | |
| depends on data rate | 01/01/70 00:00 | |
| Normally | 01/01/70 00:00 | |
| Are You Sure | 01/01/70 00:00 | |
| I would be | 01/01/70 00:00 | |
| I would be | 01/01/70 00:00 | |
| it works for me | 01/01/70 00:00 | |
| Are You Sure | 01/01/70 00:00 | |
| IIC speed - no limit | 01/01/70 00:00 | |
| nixed by other team members | 01/01/70 00:00 | |
| Multi-Proc Xface | 01/01/70 00:00 | |
| exactly | 01/01/70 00:00 | |
| Shift register (Mode 0)? | 01/01/70 00:00 | |
| Time savers | 01/01/70 00:00 |