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???
03/16/05 23:16
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#89823 - I would be
Responding to: ???'s previous message
Are you sure you need two processors?

I would be, if the load was anything significant.
I am curretly working with two 50 MIPS f126, one LPC932 and a Cypress USB host in the same box. Handling it that way is 100 times easier to do than trying to run it all on one processor. When the processors are separate, they can take care of urgent business NOW!!! you never have to wait for something else to complete. With a logical divison, you can cut the intercommunication down to almost nothing and I am doing it with a 400k IIC. Ok the LPC is a "convenience processor" used to cut PCB interconnect by 16 lines.

A previous design with a single processor suffer from the "monthly hiccup syndrome" because of being single processor supposed to run so-called multitasking. The developers did not take the little "what if a, b, c and d happen within the same 3 ns" into consideration and there is no way in hades one processor can do that.

Erik

PS Oh what a joy that the SILabs debugger can run multiple instances so you can see all 3 processors at the same time.

List of 31 messages in thread
TopicAuthorDate
Contemplating multiprocessor            01/01/70 00:00      
   fifo            01/01/70 00:00      
      and also            01/01/70 00:00      
   multiprocessor communication            01/01/70 00:00      
      ACKs            01/01/70 00:00      
      You want it all and you want it for free            01/01/70 00:00      
         Why not HW I2C or SPI            01/01/70 00:00      
            Why not HW I2C or SPI            01/01/70 00:00      
            USB ???            01/01/70 00:00      
               USB !!!            01/01/70 00:00      
                  USB            01/01/70 00:00      
                     You Correct Sir            01/01/70 00:00      
                  USB != I2C            01/01/70 00:00      
                     USB > I2C            01/01/70 00:00      
         do not multimaster            01/01/70 00:00      
   hmm            01/01/70 00:00      
   concurrence            01/01/70 00:00      
   This is why            01/01/70 00:00      
      depends on data rate            01/01/70 00:00      
   Normally            01/01/70 00:00      
   Are You Sure            01/01/70 00:00      
      I would be            01/01/70 00:00      
         I would be            01/01/70 00:00      
            it works for me            01/01/70 00:00      
      Are You Sure            01/01/70 00:00      
         IIC speed - no limit            01/01/70 00:00      
         nixed by other team members            01/01/70 00:00      
   Multi-Proc Xface            01/01/70 00:00      
      exactly            01/01/70 00:00      
   Shift register (Mode 0)?            01/01/70 00:00      
   Time savers            01/01/70 00:00      

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