Unless I'm missing sometihng ... you've missed the point of the latch in the address/data paths on P0. There's a signal called ALE, which is ADDRESS LATCH ENABLE. You're supposed to connect that to the "GATE" or Latch Enable (LE) signal on the '373 or '573 latch, whichever you choose, and the "Q" outputs from the latch will contain the ADDRESSES, hence the name, "address latch."

Now, the signals coming from P0 are addresses while ALE is HIGH, and data when it's LOW, which is most of the time.

Therefore, the bus that you've drawn, and labelled AD[0..7] should be relabelled D[0..7] and the bus that you've drawn and labelled D[0..7] should be A[0..7]. I think that will help you to understand what's going on in this circuit, assuming you mean it to be a memory-mapped I/O arrangement. If you don't intend that, then you have a lot of revision work to do.

Now, I'm working from your schematic, so I am assuming all your ADC signals not marked as active-low are positive-going. If that's not the case, then you'll have to operate on the logic accordingly.

It can be made to work with the divide-by two-configured flipflop in the ALE path to the ADC, by writing twice to the ADC. However, it will not work properly in any case, so long as you connect ALE and CLOCK together. START is intended, IIRC, to be the WRITE ENABLE function on this device, and you must not write it during a conversion. Hence, you must generate its start-conversion command by writing to it at a specific address, which latches its internal address multiplexer to that channel, steering the input to the converter, of which there is only one, and, somewhat prior to generating the EOC, (END OF CONVERSION) strobe, which you can poll if you have nothing else for the 8031 to do, until it becomes "true" or you can use that as an interrupt. If you leave the Output Enable floating, you'll never be able to read the converted value. Therefore, you must invert (e.g. with 74HC04) the RD strobe, unless the symbol is wrong, in which case you may not need to do that, in order to gate the outputs ON.

As for generating a proper START and ALE signal, I suggest you AND the inverted WR signal with A15 and drive both ALE and START with that, (use whatever address you like, but ensure that it doesn't affect anything else) and assume that the device is written at 0x8000 through 0x8007. Now connect A2, A1, and A0 directly from the address latch to the ADC. You can drive CLOCK with ALE as you've shown, but don't try to drive ALE and START with that same signal.

I don't know what that flipflop on the ALE line was intended to do, but I suspect it was intended to lengthen the ALE to the ADC. Writing twice would have made it work, OK, but not in the configuration shown. You are operating slowly enough that you don't need that flipflop.

Keep it simple, is the watchword. Since there's no external RAM and no other external I/O, you don't need a decoder, aside from the simple logic I've mentioned. You read the ADC at any address you like, but probably should not do so at the same address range, 0x800n through 0xFFFnas that at which you write it. You must latch the ADC's internal MUX address when you initiate a conversion, but I don't know whether you have to latch the address on a read. I'll let you look that up in the datasheet.

I hope this helps ... I'm getting confused ... It's been a long time since I used one of these ADC's.

RE