| ??? 04/27/06 06:03 Read: times |
#115091 - huge problem ... Responding to: ???'s previous message |
Ok ... i just ran into a problem ....
as it shows on this data sheet on (http://www.learn-c.com/adc0809.pdf) page 4, it shows the typical start pulse with and ALE pulse width of 100ns or 200ns MAX and the timing diagram on page 7. Then on this Data sheet (http://www.ee.ualberta.ca/~elliott/...rter/#EOC) is says that "The source must remain stable while it is being sampled and should contain little noise. This means it must remain stable for up to 72 clock cycles." ... now i know that i have my 8751 ALE connected to CLOCK on the ADC, which is at roughly 333kHz. To find the 72 clock cycles TIME, then i must multiply that 3 micro seconds, since its 3u seconds per instruction. But that gives me 216 micro seconds ... then since i know that the time you are looking for divided by 3u will give you the number to put on the timers. But what i am doing is just getting the 216 micro again. Sigh ... im so confused .. seems like what i was taught in school i totally forgot. My professor would smack me right now....ha. I do see a conversion time on the first data sheet of 116 micro seconds, does this have a connection to the time required to be stable? The reason i believe this is a problem because when i write the code, each line as i debug will be 3micro sec. long, and if there is a MAX of 200ns that i could i possibly get that? Does anyone understand what im trying to say? I think i am missing the meaning to something really big .... I appreciate any help ED |
