These parts are shift registers with, in one case, an input register, and in the other, an output register. Carefully study the datasheets and you'll see that they're intended to work together, if so desired.

How you clock the shift registers will determine how you should clock the parallel registers. If you want to transfer bytes, then you have to provide eight shift clocks per byte, and one register clock per byte. However, just dividing the shift clock by eight won't totally fill the bill. The PISO register must be loaded by clocking the input register at least one half-cycle before its contents must be loaded into the shift register. Then, at the precise moment when the shift register is in the state in which its last bit is at the final stage of the shift register, you must drive the shift-register-load clock high just before the shift clock occurs, but not so close to it that it fails to propagate the data from the input register. This is very tricky. For that reason, I recommend that you divide the shift clock, either in firmware or with a counter, and drive the shift-register-load clock with its carry-out ANDed with the positive phase of the shift clock. This will, unfortunately truncate the last bit. For that reason, I recommend you place a 74HC74 clocked with the SRCLK in series with your output data stream from the '597 so that all your bits will be of the correct length. This will generate a bit-time of latency but will alleviate the foreshortening of your data.

This process is not so much of a problem in the '595, since it acquires the data syncrhonously with the SRCLK, allowing you to sample the data on the edge opposite the one on which the '595 shifts the data.

The '595 is a serial-input, parallel-output device used for assembling bytes from a synchronous serial data stream and its driver clock. The '597 is a parallel-input, serial output device for disassembling bytes into a synchronous serial bit stream. Naturally, the shift clock must, in each case, be exactly synchronized with the rate at which the serialized data is being clocked at the receiver or transmitter, depending on whether it's the SIPO, or the PISO register.

I would not recommend connecting the parallel load pin of the the '597 to the ALE, since (a) the ALE occurs on each external bus cycle, and, (b) it's unlikely you'll be wanting to reload the shift register on every ALE. I could be wrong, of course, since I don't know exactly what you're doing.

A little more info would be helpful.

RE