I don't want someone's "solution" since it doesn't fit in my FPGA.

You want the most efficient serial comm there is and there is nothing more efficient than HW SPI. You may want to fine tune a detail in your FPGA, that is your option, but why screw with the UART mode 0 when HW SPI has all you want better, faster, easier.

If you do not implement HW SPI (call it acme if you want) your FPGA will fall to the floor with a big THUD in the serial I/O performance.

Erik