I'm not following ... I'm not looking for a chip that does one thing or another.

In the context of that "other" thread, I'm trying to figure out whether there's a fatal flaw in my notion that the TI and RI flags could be cleared automatically when the SBUF is read or written.

In this one, there's not much more that can be done until the Original Poster, Munaza Yousuf, comes back with more information about what his goals are and the low-level details about rate, format, etc. I think he's confused because everybody jumped him in his previous thread because he was wanting to use an 8255. I'm not sure how a PISO/SIPO pair can help him substitute for that. I'm not even sure that those parts are still available. They're good choices for this sort of thing, though.

The Mode-0 serial channel behaves VERY MUCH like the two IC's he's named, provided they're provided with the required logic to control the clocks properly and start/stop the shift clock. He may be assuming those two chips are all that's required. If that's the case, he's wrong. Left to themselves, they won't do anything, and under control of port bits, he'll be disappointed, indeed, with the data rate as compared with an 8255, which, BTW, is not at all serial, so I'm kind-of puzzled why he'd even consider the PISO/SIPO combination. I'm also puzzled as to what he's going to communicate with that will understand this logic's output.

RE