Mike:

Your idea to implement a hardware solution for a 16 byte sized "program" to implement the programming algorithm in your microcontroller is a almost as much of a zany idea as the earlier 64 byte version. Despite that this is still technically possible but not really particularly practical in the way that you have indicated that you wish to implement it. In my evaluation I still think it takes far too many gates to give any credibility to a goal to implement this with discrete logic.

Once again I cannot comment much on the legitimacy of the small program that you presented as a valid scheme to program an EEPROM. The code seems to be based upon the fact that you could write into the EEPROM from address zero, byte by byte, with no other type of handshaking or timing constraint. It clearly also assumes that the DPTR register is initialized at reset to a consistet value. I put the actual program together as a "source file" and fed it through the Keil Assembler/Linker process to produce a normal HEX file of the program data.

You can view this source code by clicking here: Source Code

The resulting HEX file of data and also with some re-formatting can be seen here: Object Data

Once again I utilized the Xilinx CPLD/FPGA device compiler and drew up a schematic that uses a brute force batch of MUXes to select 1's and 0's for each of the eight data outputs based upon the address inputs. I limited the address inputs to A0 to A3 since four bits can select 16 of the locations in the CrazyROM2. I based the 1's and 0's for the "program" based upon the compiler output that is linked above. You may see a PDF of the schematic here: CrazyROM2 Schematic File

The Xilinx tool set produced the set of equations that you may see at this link: set of equations. Notice that these equations do show a tristate buffer output enable on the CrazyROM2 outputs. This may be needed to permit the "ROM" hardware to be managed on the bus of the microcontroller to avoid contention with the normal EEPROM and RAM chips that you indicated that you intend to also have on the circuit board.

My estimate in looking at these equations is that it would take maybe 15 to 18 logic chips of the 14 and 16-pin variety to implement these equations. That is still quite a few and once again it would be a major pain if you find that the "condensed version" program needs to be changed just after you get this thing all built. On the other hand if you look at the equations closely it can be seen that these would fit with ease into a small PAL or GAL type part. I think you should give this latter idea of the use of a GAL a lot of consideration if you are still hung onto the goal of a hardware logic ROM type solution.

I have gathered all the materials for the program and the Xilinx project files together into a single ZIP file should you want to try to use the Xilinx tool set to minimize your logic. ZIP File (721K)

Good Luck. PLEASE do not take my wish for good luck or the posting of this thread to be any kind of a source of endorsment of this idea to implement a 13 byte 8051 program via 18 logic packages. It is still a CrazyROM idea.

Michael Karas