It will definitely slow the system down to less than 1/2 speed compared to the 18.432Mhz clock. so that If I am processing any logic through a logic gate, and 18.432Mhz is too fast, I can then use 8.064Mhz. and the clock I am referring to is the actual crystal itself.


I don't initially intend on using two clocks, but if the logic chips can't handle the higher speeds, then I will use 2 of them, and add a switch, so that I can flip it when I want to change speeds. This is a very simple thing to do.

Basically, my code has been crunched down to this:



But the only problem with it is that I have to add extra hardware to control the timing.

Because I am connecting this circuit to the PC's parallel port, I can use one signal from it to control the reset line, so when I am finished writing the data, I force reset to be high. I will take another signal from the parallel port to control the mode of operation. My circuit has 2 modes. 1 is the programmer mode where the above code is constantly running, and the other mode is the normal mode, where my system runs as if it was a standard SBC.

I will still have to figure out some timing, but it seems that the above code is the easiest to implement in hardware.