| ??? 03/21/07 01:46 Read: times |
#135463 - just a few words Responding to: ???'s previous message |
Keil of AVRs is IAR, they even contributed to the chip development itself (being from the neighbourhood...). No experience though, I did a few AVR projects but all asm (that's me, the C-hater...).
One thing to watch out, they ***ed, sorry, underestimated the initial design and got the SFR area too small, and are now moving SFRs to and fro "IDATA" area, so every new chip is a bit of surprise. This appears not to be your case (given the board), just a bit of warning. The pins' sharing scheme also changes wildly, the best trick so far was to move the ISP-based SPI pins from the onboard-ISP pins to some totally unrelated in Mega128, catching many on this one (me too)... :-) On the other hand, the selection of peripherals and other features on the Megas is impressive, especially given the unit cost... If you'll need to go down to asm, you'll find it fairly easy, except maybe the confusing syntax of indirectly addressed moves (LD/ST). The bit operations are a bad joke after being accustomed to the luxury of '51. Missing ADD reg,#immediate (would be addi in AVR nomenclature), and the 16 bit add/sub leaves a lot of questions behind (why did they bother at all to do it in this unusable way...). Watch out also for the limitations on registers for most of the operations - the instruction set table given at the end of datasheets is overly optimistic, I made for myself one more clearly stating the limitations. Expect more FLASH consumed than in a similar application in '51 (around 50% perhaps, plusminus). Oh yes, no hardware support for nested interrupts, but what would you expect from a non-intel design? :-) JW PS. AVR and american, is it supposed to be a joke? |
