| ??? 08/09/07 17:25 Read: times |
#143005 - It's just not that simple ... Responding to: ???'s previous message |
Jan Waclawek said:
Richard Erlacher said:
and other parts of that ilk, as they may assert reset, but the MCU potentially will ignore it and run away as Vcc decays. We ARE talking out of specs, but then, as I already said several times, the manufacturers won't put anything into the specs until the customers won't kick and punch them to do it. Of course, but isn't that the purpose of the RESET/Supervisor IC? Isn't is supposed to prevent the problems caused by out-of-spec power supply, even if it's only momentary? However, prudent manufacturers make sure that the RESET input is listened upon to as low VCC as possible - and it is not impossible at all to make it work properly the whole range, starting from zero, to VCCmax, as far as the consequences are concerned. Just as one would expect, they've protected themselves, and continue to promote the virtues of a component (several of them) that really don't do all that they could. Let's just look at the consequences side. Again, I already said, the problem is not the mcu itself - it won't get destroyed (except maybe the crap items), although, strictly speaking, the manufacturers won't guarantee that, either! (look at the formulation of what may happen if you operate outside the 5V+-10% range) - the problem is the peripherals including memories (and including the internal FLASH). ... and my position is that this is part of the problem and NOT the solution. Now in CMOS it is quite possible to block the FLASH charge pump once the reset signal comes in, even at low voltages. Sadly, they haven't done that, have they? Also, it is relatively trivial to block write access to internal RAM, once you have a valid reset signal; so that its content can be preserved under battery. They haven't done that either, have they? Also, it is relatively easy to hold the I/O pins in the default reset state, if a valid reset is present, even if the internal clock is starting to fail (due to the fact that reset is synchronous, at least the 24 clocks are required while above VCCmin, but that's fulfilled except extremely rapid powerdown - I have read about asynchronously resetted I/O pins in some '51 derivatives, but don't remember which). That's something that RESET has always done, isn't it? The same is valid for external SRAM and peripherals. Of course, it's your (the designer's) responsibility to take care of the chipselect once the reset signal is asserted (there are reset ICs which provide chipselect gating; but it's also enough to get any 74HC gate and hang it out on the battery too). Since RESET alters the state of the ports, there should be no issue with respect to external addresses during and immediately after RESET. External memory is impacted by nPSEN, nRD, and nWR. If those signals are active during RESET, something's broken. Of course, a prudent designer would want his decoders to qualify their output with a LOW (inactive) RESET. That there ARE crap mcus on the market (pitifully including '51s), that's an another issue. And that the manufacturers don't want us to dig too deep into this issue, is one more sad fact.
Nevertheless, these chips DO work, Richard, face it. Of that I have no doubt, provided that you define "work" in the terms used by their manufacturer. JW
For some time, I've been stating that (a) the problem with RESET is a product of the foolish (Intel) decision to make it (RESET) an active-high signal. However, for quite some time, too, I've been trying to get you and others who have had "experience" with the "reset problem" to tell me what specifics you've observed, not in a hand-wavy, anectotal sense, but how you've concluded that the problem that you've encountered and purport to have solved using a RESET/Supervisor IC was a RESET problem. I don't doubt for a moment that there are cases in which these components can solve a problem. I'm interested in how it's been observed to be a problem, and how it's been observed to be "fixed." I've see a number of stories, but no indication of how the problem was narrowed down to being a reset issue, and how it was observed, specifically, that the perceived reset issue no longer was present. Too often, I've gotten the impression that a circuit designer has encountered a problem, heard, from somewhere, that RESET might be cause, installed a supervisor IC because he didn't know what else to do, and, if the problem was gone, he was happy. There's really no reason to conclude that it was a RESET problem in such a case, but, because the symptoms are gone, the initial problem was not fully studied out. Sometimes, from what I've read, the problem has come back later, in the form of rarely but occasionally corrupted FLASH memory. That's why I've taken the interest in it that I've taken. RE |
