??? 08/11/07 06:09 Read: times |
#143086 - Vcc rise time Responding to: ???'s previous message |
Kai Klaas said:
Richard said:
I completely disagree with your interpretation of this statement as saying, simply, that the time constant of a 10 uF cap pulled down by 8K2 is enough. I believe that it says more than that, namely that, first and foremost, you must provide a Vcc rise time of < 1 ms, at the end of which time you must have reached and settled at a "legal" level for Vcc. I'm afraid you're wrong. The original "bible" by INTEL, which you will find here http://download.intel.com/design/MC...238302.pdf tells a more detailed story: Note, what they state: "On power up, Vcc should rise within approximately 10msec." This very lax "demand" sounds more like a recommendation than a rigid rule. It simply reflects the fact, that most tiny (and by this weak) mains transformers have no chance to charge up the storage cap in front of 7805 much faster anyway. Kai Richard, I completely agree with Kai. The Vcc rise time spec is ONLY and ONLY to make the crappy RC reset to work, there is no, NO other reason for it. Once you accept that RC reset is unsatisfactory in the majority of application and is in the datasheet just to hide the fact that the manufacturer is unable to integrate a true reset/low power detection circuitry and that you need to spend the extra $1 or whatever to ensure its proper operation (as the majority of manufacturers admit later in form of appnotes), you will stop thinking in this way. Yes, Richard, they ARE lying. Are you really surprised? Of course, you can work around this problem using a sophisticated power cycling controller (including essentially the same reference&comparator&timer combo as is in the reset IC, plus the required power components, just to prevent power out shorter than required to discharge the C of RC), and while I am not quite sure it will be satisfying during powerdown, I am absolutely sure it will by several orders of magnitude exceed the cost of $1 reset IC which you were protesting against initially... --- As for your experiment, can you please post a simplified schematics? It is not clear for me how did you combine the RC reset with the reset IC. Are you aware of the requirement that the teset IC has to "see" the SAME VCC as the mcu? Also, it is suspicious that the Dallas BRAM got corrupt as IIRC it has a builtin gate of CS during low VCC (I don't have access to the datasheets now to tell it for sure). Jan |