| ??? 09/03/03 08:46 Read: times |
#53960 - RE: MSC1210Y5 Off Chip External RAM bus Responding to: ???'s previous message |
It is indicated in datasheet http://www.gaw.ru/pdf/TI/adc/msc1210.pdf on page 21. There it also is indicated that if you use external memory (and so reset bit(s) 0/1 of HCR1) then P0/P2 can not be used as a general-purpose I/O. (and seems P3.6/P3.7 too :(
In fact, it is not an idea of 51 core but "feature" from kewl-TI-guys. |
