John,

It's pretty clear from the datasheet (SBAS203A pg. #20) that the i/o control signals and the address are generated off chip for access to the internal SRAM (notably the data portion of the access is NOT presented upon p0).

You will have to select where SRAM is to sit and then decode this area to disable external SRAM just to be safe. (an interesting question is, if the DATA portion does not propagate to P0 does an electrical conflict exist?). Prudence indicates you disable Ext. Ram during internal data access.

regards,
p