Hi,
John, reading manual once again I think:
- try map on-chip RAM into 0x8400...0x87FF via RAMMAP of Memory Control register (MCON). Maybe it helps to separate access (but I doubt);
- look at page 19 (Memory Map chapter). It says that external data memory is located from 0x8400 (if RAMMAP=1 so from 0x8800). And it also says that "Memory accesses beyond the internal range will be addressed externally via Ports 0 and 2". So the idea is: disable off-chip memory access (set both EGP0 and EGP23 bits in HCR1). This way defines P0/P2/RD/WR as general I/O pins and they should not be changed due on-chip memory access. Well, now try access data memory above 0x8400 (0x8800) --- I hope it still will be possible and P0/P2/RD/WR do it for you.
Good days!