Exactly Oleg, what I'm trying to prevent is adding more gates to decode when to enable/disable the off chip SRAM. I was looking at the MSC1210EVM schematic and it is disabling the off chip SRAM for addresses 0xF800 - 0xFFFF. This I think because the Boot ROM is mapped to these addresses. But any address below 0xF800, the off chip SRAM is enabled and accessible for anything.

Since I'm seeing ALE, *RD, *WR active does this mean for the first 1K (internal external RAM address range) of data memory, it's accessing two separate locations with the same address? I'm just trying to totally understand how the chip works.

-John G-