No.
If no off-chip memory is presented then user should set two bits of Hardware Configuration Register 1 (at chip programming time). In this case P0/P2/RD/WR are general I/O pins and do not change their states due on-chip memory access.
If there is off-chip memory and user has planed to use it then he should clear one or two of those bits (depend on 8 or 16-bit address mode). Now P0/(P2)/RD/WR are reserved for external memory access. All is simple.
But the problem of John is that in second case RD/WR signals always appear even he accesses on-chip memory address range. It should not be correct because with this way it is not possible to use both memories separately. Really, when you write to on-chip extended RAM it does write to off-chip SRAM as well. ??? Seems something wrong in hardware or programming? But if it is not an mistake then I see only one way - connect CE pin of external SRAM to an address line (for example, A15) with NOT gate. In this case, access to memory range below 0x8000 will not select off-chip SRAM, above 0x7FFF will do.