"Please provide me the source of your information."

I asked Atmel for all the timing parameters on that diagram. This is what they said:

"In fact the important point is that At Reset falling edge PSEN must be low. 24 oscillator period after reset falling edge PSEN become an output pin, so it must be release. It is recommanded to release PSEN
pin before the end of the 24 oscillator periods."

They also told me that because PSEN drives high after 24 osc. periods the device may be damaged or have its lifetime reduced if PSEN is not released within the specified time. However, whoever designs their development boards doesn't seem to know this or doesn't care.

"Moreover, for example, datasheet of AT89C51RD2/ED2 says very strange thing"

I'd have said "many, many strange things" myself.

"Seems it is mistake and should be
...thus they can be released at any time when reset input is high."

I'm not with you there - PSEN needs to be held low during the falling edge of reset. So, it has to be released when reset is low.