I am reading a book called Patterns for Time triggered Embedded Systems - Building Reliable Applications with the 8051 family of micro-controllers' by Michael J. Pont. In the first chapter he attempts to justify time triggered systems as opposed to event (interrupt) driven ones as follows:

'To see why the simultaneous occurence of two interrupts causes problems, consider what happens in the 8051 architecture in these circumstances. Like many micro-controllers, the original 8051 architecture supports two different interrupt priority levels: low and high. If two interrupts (we will call them Interrupt1 and Interrupt2) occur in rapid succession, the system will behave as follows:

A. If Interrupt1 is a low priority interrupt and Interrupt2 is a high priority interrupt: The interrupt service routine (ISR) invoked by a low priority interrupt can be interrupted by a high priority interrupt. In this case the low priority ISR will be paused, to allow the high priority ISR to be executed, after which the operation of the low priority ISR will be completed. In most cases, the system will operate correctly (provided that the two ISRs do not interfere with one another).

B. If Interrupt1 is a low priority interrupt and Interrupt2 is also a low priority interrupt: The ISR invoked by a low priority interrupt cannot be interrupted by another low priority interrupt. As a result, the response to the second interrupt will be at the very least delayed; under some circumstances it will be ignored altogether.

C. If Interrupt1 is a high priority interrupt and Interrupt2 is a low priority interrupt: The ISR invoked by the high priority interrupt cannot be interrupted by a low priority interrupt. As a result, the response to the second interrupt will be at the very least delayed; under some circumstances it will be ignored altogether.

D. If Interrupt1 is a high priority interrupt and Interrupt2 is also a high priority interrupt: The ISR invoked by a high priority interrupt cannot be interrupted by another high priority interrupt. As a result, the response to the second interrupt will be at the very least delayed; under some circumstances it will be ignored altogether.


In three cases he claims an interrupt can be ignored but nowhere does he say exactly how this could occur. If you are silly enough to use a level triggered interrupt on a short duration signal then there is the possibility to miss it if it occurs while the code is in another ISR, but apart from that I know of no mechanism that would lead to the ignoring of an interrupt.

Comments?