The relevant section of the 'bible' for INT0 and INT1 only is as follows:

When an external interrupt is generated, the flag that is generated is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. If the interrupt was level activated then the external requesting source is what controls the request flag rather that the on chip hardware.

Later the bible says:

The interrupts are sampled at S5P2 of every cycle . The samples are polled during the following cycle ....... the interrupt system will generate and LCALL to the appropriate service routine provided (it) is not blocked by one of the following:

1. An interrupt of equal or higher priotiy already in progress.

2.

3.


And lastly it says:

Note that if an interrupt flag is active but not being responded to for one of the above reasons, if the flag is not still active when the blocking condition is remved, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced IS NOT REMEMBERED. Every pooling cycle is new.


In other words, if you raise and lower a level sensitive INT0 or INT1 whilst an equal or higher priority ISR is in progress your interrupt will not be seen.

Ian