The book:
If Interrupt1 is a high priority interrupt and Interrupt2 is also a high priority interrupt: The ISR invoked by a high priority interrupt cannot be interrupted by another high priority interrupt. As a result, the response to the second interrupt will be at the very least delayed; under some circumstances it will be ignored altogether.

Michael:
This means that even in transition detection interrupt mode that pulses on the interrupt inputs that are narrower then one machine cycle are likely to be missed.

The book discuss the totally ridiculous proposition that a high priority interrupt can "kill" a low priority one which it cant, delay - yes, kill -no. That an URTOS can deley the interrupt so much that it might as well be killed is another story.

Michael discuss the correct fact that an edge triggered interrupt need a minimum pulse width. This is totally correct but not the same as the issue postulated in the book.

as to postulates in the books:
There is a saying "people that can nor write become critics" my corallary "people that can not design write books". I have seen statements in technical litterature that were so glaringly incorrect in the most basic details. One incident that come to mind was that I designed a PC interface card and used the dimensions in a very popular PC interface book (Sams) and the dimensions were WRONG by 1/4" so I had to redo the whole thing. Fortunately, I have, by now, gained enough experience and distrust of books, not to be led astray by those "authors lapses". Another issue is the "current" books that use an 8255 in every sample design and do not even mention the existence of the 22v10.

Erik