The 8051 architecture supports level and transition activated interrupts on the /INT0 and /INT1 pins. But do keep in mind that the logic behind the transition detected interrupts does not directly clock the interrupt request on the falling edge of the /INT0 or /INT1 pins. The interrupt request is set active IF the processor internal logic sees the /INTx pin high in one machine cycle and then low in the next machine cycle!!

This means that even in transition detection interrupt mode that pulses on the interrupt inputs that are narrower then one machine cycle are likely to be missed.

You have two choices to deal with this:

A) Select a microcontroller that has a clocking frequency and divider ratio (i.e. 12 clocker versus 6, 4, 3, 2, or 1X clocker chips) that has a machine cycle time that is on the order of less than half the time of the narrowest pulse time you want to detect on the /INTx pin.

B) Install an external edge triggered flip-flop that clocks on the edge of your input signal to get true edge detection. Connect the output of the flip-flop to the processor /INTx line in such manner that the clocked flip-flop asserts a low level on the /INTx pin. Then also connect another port pin output to the flip-flop PRESET or CLEAR pin as appropriate. This port pin is used in the /INTx interrupt service routine to clear out the interrupt request in the external flip-flop and arm it for the next edge clock. This approach will respond to any edge that has a pulse wide enough to clock the flip-flop. Beware that even noise spikes in the sub-nanosecond range can clock fast flip-flops so this approach demands care in the hardware design to ensure that you do not get stray unwanted interrupts due to noise and glitches.

Michael Karas