When systems are designed where it is mandatory that each and every interrupt be recognized it is essential that level type interrupts be used. In these cases the source of the interrupt request contains a request latch that is only cleared via some specific type of handshake or interrupt acknowledge from the processor that receives the interrupt. Often the interrupt request is removed via the reading of a status register in the peripheral that is generating the interrupt.

We could engage in discussion about which types of systems are classified as "high reliability" but since it invariably leads to a long session with everybody having their own opinions I'll leave this for others to comment on.

Edge triggered interrupts are popular in small embedded designs because they lend themselves to many timing and signal measurement techniques without the addition of extra hardware and/or software. The 8051 edge triggered interrupt mechanism, with its auto-clearing interrupt status bit, was specifically designed by Intel permit ISR processing with an absolute minimum number of instructions needed.

Michael Karas