Nothing is solved! Jan already tried to explain, why your scheme will not work reliably. I try it again:
When you set P1.3 high, then output emits logic high level. In order to do this, standard quasi-bidirectional port driver topology turns-on an internal active pull-up. So, when you put a load to the port pin, in your case 4k7 resistor, then this internal active pull-up can source a current of up to 750µA. This will cause a voltage drop of up to 750µA x 4k7 = 3.53V, which is way too high to make the port pin assume logic low level!
The only remedy is to drastically reduce the load resistance seen to ground. Load resistance must be smaller than 2V / 750µA = 2k7, better, even lower than 0.9V / 750µA = 1k2, where 0.9V is the maximum input low voltage.

Your scheme, which seems to look like that



does also show an additional disadvantage:
Your 4k7 resistor forms a voltage divider in combination with Rx. In order to keep the level at output of comparator high, Rx must be kept very low, which heavily increases current consumption, especially if the 4k7 resistor needs to be decreased to less than 1k2, as demonstrated above!
A better approach is shown below:



Here the load resistance seen by P1.3 is adequately low (1k2). The 200R resistor is for protection purpose, if you eroneously set P1.3 low during experimentation.
This circuit, which only needs one transistor shows the disadvantage of increased current consumption. A better solution is to use two inverter stages for the level translation, as shown below.



Another option to accomplish this level translation is to use MC14504 chip, for instance.

Kai